COURTAY Antoine – Associate Professor

IRISA – GRANIT Team

ENSSAT – University of Rennes 1

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Patents

 

O. Sentieys, A. Courtay, C. Huriaux and S. Pillement

Method and Device for Programming a FPGA

France, Patent Reference 14305143.1, 2014

 

A. Courtay, J. Laurent, O. Sentieys and N. Julien.

Procédé et dispositif de codage, système électronique et support d’enregistrement associés.

Patent Pending, Reference BFF 08P0103/HC, 2008

 

Journal Papers

 

A. Courtay, J. Laurent and O. Sentieys.

Spatial Switching data coding technique analysis and improvements for interconnect power consumption optimization.

Journal of Low Power Electronics (JOLPE), Vol 6, No 1, pages 32-43, 2010

 

A. Courtay, O. Sentieys, J. Laurent and N. Julien.

High-Level Interconnect Delay and Power Estimation.

Journal of Low Power Electronics (JOLPE), Vol 4, No 1, pages 21-33, 2008

 

International Conferences Papers

 

 

B. Janßen, F. Schwiegelshohn, M. Koedam, L. Masing, S. Werner, C. Huriaux, A. Courtay, E. Wheatley, K. Goossens, F. Lemonnier, P. Millet, J. Becker, O. Sentieys and M. Hübner

Designing Applications for Heterogeneous ManyCore Architectures with the FlexTiles Platform.

In the 25th IEEE International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS) , 2015

 

G. M. Hoang, M. Gautier and A. Courtay

Cooperative-cum-Constrained Maximum Likelihood Algorithm for UWB-based Localization in Wireless BANs

In the IEEE International Conference on Communications (ICC), London, United Kingdom, 2015

 

C. Huriaux,  A. Courtay and O. Sentieys

Design Flow and Run-Time Management for Compressed FPGA Configurations

In Design, Automation and Test in Europe (DATE), 2015

 

Q. H. Le, E. Casseau and A. Courtay

Place Reservation Technique for Online Task Placement on a Multi-context Heterogeneous Reconfigurable Architecture

In the International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 2014

 

C. Huriaux, O. Sentieys and A. Courtay

An FPGA Configuration Stream Architecture Supporting Seamless Hardware Accelerator Migration

In the DATE 2013 Workshop on Reconfigurable Computing V2.0: The Next Generation of Technology (DATE Workshop),Grenoble, France, 2013

 

A. Courtay, A. Pegatoquet, M. Auguin and C. Chabaane.

Wireless Sensor Network Node Global Energy Consumption Modelization.

In the Proceedings of the IEEE Design and Architectures for Signal and Image Processing Conference (DASIP), pages 54-61, Edinburgh, Scottland, 2010

 

A. Courtay, J. Laurent, O. Sentieys and N. Julien.

Interconnect Explorer: A High-level Power Estimation Tool for On-Chip Interconnects.

In the User Track of the IEEE Design Automation Conference (DAC), San Fransisco, USA, 2009

 

A. Courtay, E. Boutillon and J. Laurent

A Convolutional Code for On-chip Interconnect Crosstalk Reduction.

In the Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pages 145-148, Taipei, Taiwan, 2009

 

A. Courtay, J. Laurent, O. Sentieys and N. Julien.

On-chip interconnects energy consumption: High-level estimation and architectural optimizations.

In the PhD forum of the Design, Automation & Test in Europe conference (DATE), Nice, France, 2009

 

A. Courtay, J. Laurent, O. Sentieys and N. Julien.

Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses.

In the Proceedings of the IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Lisbon, Portugal, 2008

Published in Springer Verlag Lecture Notes in Computer Science, LNCS5349, pages 359-358

 

A. Courtay, J. Laurent, N. Julien and O. Sentieys.

New directions in interconnect performance optimization.

In the Proceedings of the 3rd IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pages 1-6, Tozeur, Tunisia, 2008

 

A. Courtay, O. Sentieys, J. Laurent and N. Julien.

Interconnect Explorer : a High-Level Estimation Tool for On-Chip Interconnects.

In the University Booth of the SAME Forum (SAME), Nice, France, 2008

 

National Conferences Papers

 

M. Gautier, A. Courtay and G. M. Hoang

Estimation coopérative et sous contraintes pour la localisation dans les réseaux de capteurs corporels

In the GRESTI symposium (GRETSI), Lyon, France, 2015

 

Q. H. Le, E. Casseau and A. Courtay

Placement en Ligne de Tâches sur Architecture Dynamiquement Reconfigurable Hétérogène

In GDR SOC SIP symposium, Paris, France, 2014

 

Q. H. Khuat, Q. H. Le Quang, D. Chillet, A. Courtay and E. Casseau
Ordonnancement Spatio-Temporel 3D minimisant le coût de communications entre tâches
In the Poster session of the GRESTI symposium (GRETSI), Brest, France, 2013

 

A. Courtay, J. Laurent, N. Julien and O. Sentieys.

Modélisation, Estimation et Optimisation de la consommation des interconnexions dans les SOC.

In the 2nd GDR SOC SIP symposium, Paris, France, 2008

 

A. Courtay, J. Laurent, N. Julien and O. Sentieys.

Estimation et optimisation de la consommation des interconnexions dans les SOC.

In the 1st GDR SOC SIP symposium, Paris, France, 2007

 

A. Courtay, J. Laurent, O. Sentieys and N. Julien.

Modélisation et estimation de la consommation des interconnexions dans les SOC.

In the Proceedings of the Faible Tension Faible Consommation conference (FTFC), pages 121-125, Paris, France, 2007

 

A. Courtay, O. Sentieys and N. Julien.

Interconnexions et consommation : où en sommes nous ?

In the 4th MajecSTIC conference (MajecSTIC), Lorient, France, 2006

 

PhD Thesis

 

A.Courtay

Consommation d’énergie dans les interconnexions sur puce : Estimation de haut niveau et optimisations architecturales.

Presented on November 25, 2008.