CASSEAU Emmanuel - Publications
IRISA Lab., CAIRN team
ENSSAT, Lannion, France.
Scheduling and mapping :
● P. Dobias, E. Casseau, and O. Sinnen, “Comparison of Different Methods Making Use of Backup Copies for Fault-Tolerant Scheduling on Embedded Multiprocessor Systems”, Conference on Design and Architectures for Signal and Image Processing (DASIP), Porto, Portugal, pp.1-6, October 10-12, 2018.
● P. Dobias, E. Casseau, and O. Sinnen, “Restricted Scheduling Windows for Dynamic Fault-Tolerant Primary/Backup Approach-Based Scheduling on Embedded Systems”, SCOPES '18: 21th International Workshop on Software and Compilers for Embedded Systems, Sankt Goar, Germany, May 28-30, 2018. https://dl.acm.org/citation.cfm?doid=3207719.3207724
● Q.H Le, E. Casseau, A. Courtay,, “Place Reservation Technique for Online Task Placement on a Multi-context Heterogeneous Reconﬁgurable Architecture”, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), Cancun, Mexico, December 8-10, 2014. https://ieeexplore.ieee.org/document/7032553
● H. Yviquel, E. Casseau, M. Raulet, P. Jääskeläinen, J. Takala, “Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms”, 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy, pp. 732-737, September 4-6, 2013.
● E. Raffin, C. Wolinski, F. Charot, E. Casseau, A. Floc’h, K. Kuchcinski, S. Chevobbe, S. Guyetant, “Scheduling, Binding and Routing System for a Run-Time Reconﬁgurable Operator Based Multimedia Architecture”, International Journal of Embedded and real-Time Communication Systems, IJERTCS, Volume 3, Issue 1, pp. 1-30, 2012.
● H. Yviquel, E. Casseau, M. Wipliez, M. Raulet, ”Efficient Multicore Scheduling of Dataflow Process Networks”, IEEE Workshop on Signal Processing Systems, SiPS 2011, Beirut, Lebanon, October 4-7 2011.
Algorithms / techniques for high-level synthesis based design methodologies :
● C. Xiao, S. Wang, W. Liu, E. Casseau, "Parallel Custom Instruction Identification for Extensible Processors", Journal of Systems Architecture, Elsevier, Volume 76, pp 149-159, May 2017.
● S. Wang, C. Xiao, W. Liu, E. Casseau, “A comparison of heuristic algorithms for custom instruction selection”, Microprocessors and Microsystems : Embedded Hardware Design (MICPRO), Elsevier, Volume 45, Part A, pp 176-186, August 2016.
● S. Wang, C. Xiao, W. Liu, E. Casseau, X. Yang, “Selecting Most Proﬁtable Instruction-Set Extensions Using Ant Colony Heuristic”, Conference on Design and Architectures for Signal and Image Processing, DASIP 2015, Cracow, Poland, pp.-, September 23-25, 2015. https://ieeexplore.ieee.org/document/7367250
● C. Xiao, E. Casseau, S. Wang, W. Liu, “Automatic custom instruction identification for application-specific instruction set processors”, Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, Volume 38, Issue 8, Part B, November 2014, pp 1012-1024.
● X. Xiao, E. Casseau, “Improving High-Level Synthesis Effectiveness Through Custom Operator Identification”, IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, June 1-5, pp 161-164, 2014. https://ieeexplore.ieee.org/document/6865090
● C. Xiao, E. Casseau, "Exact Custom Instruction Enumeration for Extensible Processors", Integration, the VLSI Journal, Elsevier, Volume 45, Issue 2, pp 263-270, June 2012, http://www.sciencedirect.com/science/article/pii/S0167926011001003
● E. Casseau, B. Le Gal, “Design of Multi-Mode Application-Specific Cores Based on High-Level Synthesis”, Integration, the VLSI Journal, Elsevier, Volume 45, Issue 1, pp. 9-21, January 2012. http://www.sciencedirect.com/science/article/pii/S0167926011000617
● C. Xiao, E. Casseau, “An Efficient Algorithm for Custom Instruction Enumeration”, 21st Great Lakes Symposium on VLSI (GLSVLSI), Lausanne, Switzerland, May 2-4, 2011.
● B. Le gal, E. Casseau, “Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis”, Journal of Signal Processing Systems, Springer, Volume 62, Issue 3, pp. 341-357, 2011.
● B. Le gal, E. Casseau, “Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design”, EURASIP Journal on Advances in Signal Processing, special issue : Quantization of VLSI Digital Signal Processing Systems, vol. 2011, Article ID 927670, 2011. doi:10.1155/2011/927670.
HW architectures and design :
● I. Wali, E. Casseau, A. Tisserand, “An Efﬁcient Framework for Design and Assessment of Arithmetic Operators with Reduced-Precision Redundancy”, Conference on Design and Architectures for Signal and Image Processing (DASIP), Dresden, Germany, pp.1-6, September 27-29, 2017. https://ieeexplore.ieee.org/document/8122117
● J. Métairie, A. Tisserand, E. Casseau, “Small Multiplication-Inversion Unit for Normal Basis Representation in GF(2^m)”, ISVLSI 2015, Montpellier, France, 8-10 July, 2015. https://ieeexplore.ieee.org/document/7309607
● S. Khan, E. Casseau, D. Menard, “High performance Discrete Cosine Transform (DCT) operator using multimedia oriented subword parallelism (SWP)”, Advances in Computer Engineering, Hindawi, Article ID 405856, 2015,
● S. Khan, E. Casseau, “High-performance motion estimation operator using multimedia oriented subword parallelism”, Journal of Communication and Computer, David publishing Company, Vol. 9, No. 1, pp. 1-14, 2012, http://www.davidpublishing.com/show.html?3593
● D. Menard, H-N. Nguyen, F. Charot, S. Guyetant, J. Guillot, E. Raffin, E. Casseau, “Exploiting reconfigurable SWP operators for multimedia applications”, 36th International Conference on Acoustics, Speech and Signal Processing (ICASSP), Prague, Czech Republic, May 22-27, pp. 1717-1720, 2011.
Design approaches for dataflow programs :
● M.T. Tran, M. Gautier, E. Casseau, "On the FPGA-based implementation of a flexible waveform from a high-level description: Application to LTE FFT case study", EAI International Conference on Cognitive Radio Oriented Wireless Networks (Crowncom 2016), Grenoble, France, May 30 - June 1, 2016, pp. 545-557, 2016. https://link.springer.com/chapter/10.1007%2F978-3-319-40352-6_45
● K.J.M. Martin, J-P. Diguet, Y. Eustache, D-T. Ngo, E. Casseau, Y. Oliva, "Compa backend: a Dynamic Runtime for the execution of dataflow programs onto multi-core platforms", Conference on Design and Architectures for Signal and Image Processing, DASIP 2015, Demo Night, Cracow, Poland, September 23-25, 2015. https://ieeexplore.ieee.org/document/7367246
● H. Yviquel, A. Sanchez, P. Jääskeläinen, J. Takala, M. Raulet, E. Casseau, “Embedded multi-core systems dedicated to dynamic dataflow programs”, The Journal of Signal Processing Systems, Springer, Volume 80, Issue 1, pp 121-136, July 2015., DOI 10.1007/s11265-014-0953-5, http://link.springer.com/article/10.1007/s11265-014-0953-5.
● M. Gautier, E. Casseau, H. Yviquel, G.S. Ouedraogo, M. Raulet, O. Sentieys, “Rapid prototyping for Video Coding over Flexible Radio Links”, in “Multimedia Over Cognitive Radio Networks: Algorithms, Protocols, and Experiments”, Chapter 20, pp. 439-458, Ed.: F. Hu, S. Kumar, Publisher: CRC Press, 2014, ISBN 9781482214857,
● H. Yviquel, E. Casseau, M. Wipliez, J. Gorin, M. Raulet, “Classification-based optimization of dynamic dataflow programs”, in "Advancing Embedded Systems and Real-Time Communications with Emerging Technologies", Chapter 12, pp. 283-302, Ed.: S. Virtanen, IGI Global, 2014, ISBN13: 9781466660342,
● Y. Oliva, E. Casseau, K. Martin, P. Bomel, J-P. Diguet, H. Yviquel, M. Raulet, E. Raffin, L. Morin, “Orcc’s Compa-Backend demonstration”, Conference on Design and Architectures for Signal and Image Processing”, DASIP 2014, Demo Night, Madrid, Spain, October 8-10, 2014.
● K. Martin, J-P. Diguet, E. Casseau, Y. Oliva, “Dataflow program implementation onto a heterogeneous multiprocessor platform”, Workshop on MEthods and TOols for Dataflow PrOgramming, METODO 2014, Madrid, Spain, October 7, 2014.
● H. Yviquel, A. Sanchez, P. Jääskeläinen, J. Takala, M. Raulet, E. Casseau “Efficient Software Synthesis of Dynamic Dataflow Programs”, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Florence, Italy, 4-9 May, pp 4988-4992, 2014.
● H. Yviquel, J. Boutellier, M. Raulet, E. Casseau, “Automated design of networks of Transport-Triggered Architecture processors using Dynamic Dataflow Programs”, Signal Processing: Image Communication (Elsevier), Special Issue on Recent Advances on MPEG Codec Configuration Framework, Volume 28, Issue 10, pp 1295-1302, November 2013.