Emmanuel CASSEAU

Univ Rennes

IRISA Lab., TARAN team
ENSSAT, 6 rue de Kerampont, BP 80518, 22305 LANNION Cedex


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Reasearch activities        Teaching activities

Emmanuel Casseau received the Ph.D Degree in Electronic Engineering from UBO University, Brest, France, in 1994 and the MS Degree in Electrical Engineering in 1990. From 1994 until 1996 he was a research engineer in ENST Bretagne, a graduate engineering school in France, where he developed high-speed Viterbi decoder architectures for turbo-code VLSI implementations. From 1996 until 2006 he was an Associate Professor in the Electronic Department at the University de Bretagne Sud, Lorient, France, where he led the IP project of the Lester lab. He is a Professor in Taran team at INRIA/IRISA Lab., ENSSAT graduate engineering school, University of Rennes, Lannion, France. From August 2016 until July 2017, he was an academic researching visitor in the Parallel and Reconfigurable Computing Group, Department of Electrical and Computer Engineering, University of Auckland, New Zealand. He is currently the Head of the Department of Electronic Engineering (namely Department of “Digital Systems Engineering”), ENSSAT Engineering Graduate School, Lannion, France. His research interests include system design, high-level synthesis, mapping/scheduling techniques, fault-tolerant techniques and design, reconfigurable architectures and FPGA-based accelerators.

Open positions


See my DBLP entry  or  ResearchGate entry  or  HAL open science entry .

PhD students :

PhD graduates since I’m in IRISA Lab :

Teaching activities

Current taught modules :

·        Computer architecture : It introduces the main concepts of computer architecture: Von Neumann architecture, pipeline-based architecture concept, cache memory, branch prediction.

·        Field-Programmable Gate Arrays (FPGAs) : This course covers the main basics of (re)configurable logic and presents FPGAs. Main FPGA features and elements are investigated.  Design steps are also introduced.

·        Hardware description language : It introduces the main concepts behind HW description languages. VHDL is investigated. Labs are based around the Quartus Prime framework (Intel) and ModelSim. A project in the audio processing domain is carried out targeting DE10-Lite platform.


·        High-level synthesis : This course is aimed at introducing the goal of high-level synthesis (HLS) for dataflow based applications and covers HLS main steps: scheduling, allocation, and binding.

·        Real time design methodology : This course is aimed at developing real time (RT) applications. Petri nets and SART methodology are investigated. VxWorks RT operating system (WindRiver) is used for labs.

ICT Master 2 students (embedded system option), Hanoi, Vietnam, 2013