Emmanuel CASSEAU

INRIA/IRISA, UMR 6074
CAIRN
ENSSAT, 6 rue de Kerampont, BP 80518, 22305 LANNION Cedex
FRANCE

 

Contact      Casseau Emmanuel


Home page

http://perso.univ-rennes1.fr/emmanuel.casseau

Phone: 

+33 (0)2 96 46 91 76

e-mail:

to_remove_emmanuel.casseau@irisa.fr

 

 

Reasearch activities    Teaching activities

Open positions


Emmanuel Casseau received the Ph.D Degree in Electronic Engineering from UBO University, Brest, France, in 1994 and the MS Degree in Electrical Engineering in 1990. From 1994 to 1996 he was a research engineer in ENST Bretagne, a graduate engineering school in France, where he developed high-speed Viterbi decoder architectures for turbo-code VLSI implementations. From 1996 to 2006 he was an Associate Professor in the Electronic Department at the University de Bretagne Sud, Lorient, France, where he led the IP project of the Lester lab. He is a Professor at INRIA/IRISA Lab., ENSSAT graduate engineering school, University of Rennes1, Lannion, France. He is currently a Visitor in the Parallel and Reconfigurable Computing Group, Department of Electrical and Computer Engineering, University of Auckland, New Zealand. His research interests include system design, high-level synthesis, mapping/scheduling techniques, reconfigurable architectures and FPGA-based accelerators.

Publications


Reasearch activities :

Funding :

ˇ         Reliasic (2014-2018) in collaboration with Lab-STICC and IETR/SNC. One of the most critical challenges of the ITRS overall design technology is fault-tolerant computation. The increase in integration density and the requirement of low-energy consumption can only be sustained through low-powered components, with the drawback of a looser robust-ness against transient errors. In the near future, electronic gates to process information will be inherently unreliable. In this project, we want to address this problem with a bottom-up approach, starting from an existing application (a GPS receiver) as a use case and adding some redundant mechanisms to allow the GPS receiver to be tolerant to transient errors due to low voltage supply. During this project, we will develop knowledge at several levels: the eect of low voltage at transistor level, application of robust non-conventional arithmetic, the downstream impact of gate level errors on arithmetic and functional operation, refinement of high level specification (reliability and quality of service) to low level arithmetic and functional requirements.

ˇ         COMPA (2011-2015) in collaboration with CAPS Entreprise, IETR, Lab-STICC, Modae Technology and TI France. Aim of the ANR COMPA project is to propose a methodology and a design framework for running applications specified based on the dataflow process network model on a heterogeneous multi-core platform for embedded systems. CAL actor language, developed in the Ptolemy project, will be used as the specification language. More specifically, as we target reconfigurable video coding (RVC) standard, we will use the RVC-CAL subset. The aim of the project is to provide solutions to adapt at runtime the mapping and scheduling of the application over a multi-core architecture. The adaptation can be addressed by changing the number of used cores and/or by changing the way cores are interconnected. For experiments, the hardware platform will be an FPGA implementing one ARM CPU and several processor cores.

ˇ         S2S4HLS (2009-2012) in collaboration with ST Microelectronics : High-level synthesis HLS tools start to be used for industrial designs. HLS is analogous to software compilation transposed to the hardware domain. From an algorithmic behavior of the specification, HLS tools automate the design process and generate a register transfer level RTL architecture taking into account user-specified constraints. However design performance still depends on designer's skill to write appropriate source code. S2S4HLS project intends to process source code transformations to guide synthesis and lead to more efficient designs.

ˇ         ROMA (2007-2010): The ROMA project proposes to develop a reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its computing structure to video dedicated computation patterns that can be speed-up and/or power efficient. On the contrary of previous attempts to design reconfigurable processors, which have focused on the definition of complex interconnection network between simple operators, a pipeline-based of evolved low-power coarse grain reconfigurable operators is investigated to avoid traditional overhead, in reconfigurable devices, related to the interconnection network. The adaptation of the processor datapath can be done dynamically in case of several consecutive functions to speed. A particular attention is given to the operator such as their granularity to match the domain-specific (video) computation patterns as well as the number system and the word-length used for the representation of the data.

Open positions

PhD students :

PhD graduates :

Publications


Teaching activities

Current taught modules :

ICT Master 2 students (embedded system option), Hanoi, Vietnam, 2013