CASSEAU  Emmanuel       -         Selected papers
INRIA/IRISA – CAIRN
ENSSAT, University of Rennes1, Lannion, France.

Design approaches :

  • E. Casseau, B. Le Gal, “Design of Multi-Mode Application-Specific Cores Based on High-Level Synthesis”, Integration, the VLSI Journal, Elsevier, Volume 45, Issue 1, pp. 9-21, January 2012.
  • E. Raffin, C. Wolinski, F. Charot, E. Casseau, A. Floc’h, K. Kuchcinski, S. Chevobbe, S. Guyetant, “Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture”, International Journal of Embedded and real-Time Communication Systems, IJERTCS, Volume 3, Issue 1, pp. 1-30, 2012.
  • H. Yviquel, E. Casseau, M. Wipliez, M. Raulet, ”Efficient Multicore Scheduling of Dataflow Process Networks”, IEEE Workshop on Signal Processing Systems, SiPS 2011, Beirut, Lebanon, October 4-7 2011.
  • A. Banciu, E. Casseau, D. Menard, T. Michel, "Stochastic Modeling for Floating-point to Fixed-point Conversion”, IEEE Workshop on Signal Processing Systems, SiPS 2011, Beirut, Lebanon, October 4-7 2011.
  • B. Le gal, E. Casseau, “Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis”, Journal of Signal Processing Systems, Springer, Volume 62, Issue 3, pp. 341-357, 2011.
  • D. Menard, H-N. Nguyen, F. Charot, S. Guyetant, J. Guillot, E. Raffin, E. Casseau, “Exploiting reconfigurable SWP operators for multimedia applications”, 36th International Conference on Acoustics, Speech and Signal Processing (ICASSP), Prague, Czech Republic, May 22-27, pp. 1717-1720, 2011.
  • B. Le gal, E. Casseau, “Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design”, EURASIP Journal on Advances in Signal Processing, special issue : Quantization of VLSI Digital Signal Processing Systems, vol. 2011, Article ID 927670, 2011. doi:10.1155/2011/927670.
  • C. Xiao, E. Casseau, “An Efficient Algorithm for Custom Instruction Enumeration”, 21st Great Lakes Symposium on VLSI (GLSVLSI), Lausanne, Switzerland, May 2-4, 2011.
  • A. Banciu, E. Casseau, D. Menard, T. Michel, “A Case Study of the  Stochastic Modeling Approach for Range Estimation”, Conference on Design and Architectures for Signal and Image Processing, DASIP 2010, Edinburgh, UK, October 26-28, pp.301-308, 2010.
  • E. Raffin, C. Wolinski, F. Charot, K. Kuchcinski, S. Guyetant, S. Chevobbe, E. Casseau, “Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture”, Conference on Design and Architectures for Signal and Image Processing, DASIP 2010, Edinburgh, UK, October 26-28, pp.12-19, 2010.
  • E. Casseau, B. Le Gal, " High-Level Synthesis for the Design of FPGA-based Signal Processing Systems", International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS, Samos, Greece, pp.25-32, July 20-24, 2009.
  • B. Le Gal, E. Casseau, S. Huet, " Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis", IEEE Transactions on Very Large Scale Integration Systems, Vol.16, No.11, pp.1454-1464, November 2008.
  • B. Le Gal, E. Casseau, C. Andriamisaina, "Synthèse de haut niveau tenant compte de la dynamique des traitements", TSI, Technique et Science Informatiques, Lavoisier, Vol.27, No.9-10, pp 1129-1154, 2008.
  • C. Chavet, P. Coussy, C. Andriamisaina, E. Casseau, E. Juin, P. Urard, E. Martin, "A design flow dedicated to multi-mode architectures for DSP applications", IEEE/ACM Int. Conf. on Computer-Aided Design, ICCAD, San Jose, CA, USA, pp.604-611, November 2007.
  • S. Huet, S. LeNours, O. Pasquier, E. Casseau, "Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications", Forum on specification & Design Languages, FDL  2007, Barcelona, Spain, September 2007.
  • P. Coussy, E. Casseau, P. Bomel, A. Baganne, E. Martin, " Constrained Algorithmic IP Design for System-On-Chip", Integration, the VLSI journal, Volume 40, Issue 2, pp. 94-105, February 2007.
  • C. Andriamisaina, B. Le Gal, E. Casseau," Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems", IEEE System on Chip Conference, SOCC 2006, Austin, USA, September 2006.
  • S. Huet, E. Casseau, O. Pasquier, " Hardware Communication Refinement in Digital Signal Processing, Modelling Issues", FDL 2006, Forum on specification & Design Languages, , TU Darmstadt, Germany, September 2006.
  • S. Huet, E. Casseau, O. Pasquier, "Design exploration and HW/SW rapid prototyping for real time system design", SME Technical Paper, Society of Manufacturing Engineers, Ref. TP06PUB32, www.sme.org, May 2006.
  • P. Coussy, E. Casseau, P. Bomel, A. Baganne, E. Martin, "A Formal Method for Hardware IP Design and Integration under I/O and Timing Constraints", ACM Transactions on Embedded Computing Systems (TECS), Vol.5 , Issue 1, pp 29-53, February 2006.
  • B. Le Gal, E. Casseau, C. Andriamisaina, E. Martin, "Dynamic memory acess managment and address computation for dataflow applications", VLSI-SOC 2005, IFIP International Conference on Very Large Scale Integration, Perth, Australia, October 2005.
  • E. Casseau, B. Le Gal, P. Bomel, C. Jégo, S. Huet, E. Martin, "C-based rapid prototyping for digital signal processing", EUSIPCO 2005, European Signal Processing Conference, Antalya, Turquey, September 2005.

 

HW design :

  • S. Khan, E. Casseau, “High-performance motion estimation operator using multimedia oriented subword parallelism”, Journal of Communication and Computer, David publishing Company, Vol. 9, No. 1, pp. 1-14, 2012.
  • C. Beaumin, O. Sentieys, E. Casseau, A. Carer, “A Coarse-Grain Reconfigurable Hardware Architecture for RVC-CAL-based Design”, Conference on Design and Architectures for Signal and Image Processing, DASIP 2010, Edinburgh, UK, October 26-28, pp.161-168, 2010.
  • S. Khan, E. Casseau, D. Menard, "High speed reconfigurable SWP operator for multimedia processing using redundant data representation", IJISCE, Int. Journal of Information Sciences and Computer Engineering, Vol. 1, No. 1, pp.45-52, may 2010.
  • S. Khan, D. Menard, E. Casseau, "Reconfigurable SWP Operator for Multimedia Processing", 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009, pp.199-202, Boston, USA, July 7-9, 2009.
  • D. Menard, E. Casseau, S. Khan, O. Sentieys, S. Chevobbe, S. Guyetant, R. David, "Reconfigurable Operator Based Multimedia Embedded Processor", International Workshop of Applied Reconfigurable Computing, ARC 2009, LNCS 5453, pp.39-49, Karlsruhe, Germany, March 16-18, 2009.
  • G. Savaton, E. Casseau, E. Martin, "Design of a Flexible 2-D Discrete Wavelet Transform IP Core for JPEG2000 Image Coding in Embedded Imaging Systems" Signal Processing, Elsevier Science, Vol.86, Issue 7, pp.1375-1399, July 2006.
  • F. Sayadi, E. Casseau, M. Atri, M. Marzougui, R. Tourki, E. Martin, "G729 voice decoder design", Journal of VLSI Signal Processing, Springer, Vol.42, No.2, pp 173-184, February 2006.
  • E. Casseau, B. Le Gal, C. Jégo, N. Le Héno, E. Martin, "Reed-Solomon behavioral virtual component for communication systems", ISCAS 2004, IEEE International Symposium on Circuits and Systems, Vancouver, Canada, May 2004.