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Emmanuel CASSEAU Univ
Rennes INRIA,
CNRS |
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Contact Casseau
Emmanuel
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Reasearch
activities Teaching activities
Emmanuel Casseau received the Ph.D
Degree in Electronic Engineering from UBO University, Brest, France, in 1994
and the MS Degree in Electrical Engineering in 1990. From 1994 until 1996 he
was a research engineer in ENST Bretagne, a graduate engineering school in
France, where he developed high-speed Viterbi decoder architectures for
turbo-code VLSI implementations. From 1996 until 2006 he was an Associate
Professor in the Electronic Department at the University de Bretagne Sud, Lorient,
France, where he led the IP project of the Lester lab. He is a Professor in Taran team at INRIA/IRISA Lab., ENSSAT graduate engineering school, University of Rennes, Lannion,
France. From August 2016 until July 2017, he was an academic researching
visitor in the Parallel and Reconfigurable
Computing Group, Department of Electrical and Computer Engineering,
University of Auckland, New Zealand. He is currently the Head of the Department
of Electronic Engineering (namely Department of “Digital Systems
Engineering”), ENSSAT Engineering
Graduate School, Lannion, France. His research interests include system design,
high-level synthesis, mapping/scheduling techniques, fault-tolerant techniques
and design, reconfigurable architectures and FPGA-based accelerators.
Publications
See my DBLP entry
or ResearchGate
entry or HAL
open science entry .
PhD students :
- B. Rossigneux
(2022-2025) co-supervised by I. Kucher
and V. Lorrain : Adapt sparsity to hardware in neural networks. Keywords : compressors, memory
requirements, quantization.
- H. Amara (2022-2025) co-supervised by D. Chillet and C.
Killian : Detection and countermeasures for DoS attack in NoC-based SoC using machine learning. Keywords :
network on chip, denial of service attacks, machine learning.
- S. Lee (2021-2024) co-supervised by A. Kritikakou and R.
Salvador : Design of on-board heterogeneous embedded systems for space
applications. Keywords : system on chip, design space exploration,
space applications.
PhD graduates since I’m in IRISA Lab :
- V. L. Nguyen Huu
(2020-2022) co-supervised by L. d’Orazio
: Hardware acceleration, an application to big data analytics in security
monitoring. Keywords : FPGA acceleration, data management systems,
semantic caching.
- M. Cui (2018-2022) co-supervised
by A. Kritikakou : Energy-Quality-Time Fault
Tolerant Task Mapping on Multicore Architectures. Keywords : mapping and scheduling, QoS, WCET, fault-tolerance,
multicore architectures.
- P. Dobias (2017-2020) : Online Fault Tolerant Task
Scheduling for Real-Time Multiprocessor Embedded Systems. Keywords :
fault-tolerance, online mapping and scheduling, multi-processor platforms,
Real-Time Embedded Systems, CubeSats.
- M. T. Tran (2013-2018) co-supervised by M. Gautier : Towards Hardware Synthesis of a
Flexible Radio from a High-Level Language. Keywords : software defined radio, high-level synthesis, FPGA,
dynamic reconfiguration.
- J. Metairie (2012-2016) co-supervised by A. Tisserand
: Contributions to GF(2^m) Operators for
Elliptic Curves Based Cryptography. Keywords : arithmetic operator design, elliptic curve
cryptography, side channel attacks.
- H. Yviquel (2010-2013) co-supervised by M. Raulet (IETR Rennes) : From dataflow-based video
coding tools to dedicated embedded multi-core platforms. Keywords : Reconfigurable Video Coding (RVC), dataflow programs, multi-core
platform, TTA processors.
- T. Chabrier (2009-2013)
co-supervised by A. Tisserand : Arithmetic Recodings
for ECC Cryptoprocessors with Protection against
Side Channel Attacks. Keywords : arithmetic operator design, elliptic curve
cryptography.
- C. Xiao (2009-2012) : Custom
operator identification for high level synthesis . Keywords : subgraph enumeration, subgraph selection, code
transformation.
- A. Banciu (2008-2012)
: A stochastic approach for the range evaluation. In collaboration with ST
Microelectronics. Keywords : range
estimation, fixed-point arithmetic, digital signal processing systems.
- S. Khan (2007-2010) : Development of High Performance Hardware Architectures for
Multimedia Applications. Keywords
: multimedia applications, subword
parallelism (SWP), VLSI design.
Current taught modules :
- Basics of digital electronics : This course is aimed at introducing digital
electronics from scratch: number systems, Boolean algebra, logic gates,
combinational & sequential circuits, ...
·
Computer
architecture : It
introduces the main concepts of computer architecture: Von Neumann
architecture, pipeline-based architecture concept, cache memory, branch
prediction.
·
Field-Programmable
Gate Arrays (FPGAs) : This course covers the main basics of (re)configurable
logic and presents FPGAs. Main FPGA features and elements are
investigated. Design steps are also
introduced.
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·
Hardware
description language : It introduces the main concepts behind HW
description languages. VHDL is investigated. Labs are based around the
Quartus Prime framework (Intel) and ModelSim. A
project in the audio processing domain is carried out targeting DE10-Lite
platform. |
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·
High-level
synthesis : This
course is aimed at introducing the goal of high-level synthesis (HLS) for
dataflow based applications and covers HLS main steps: scheduling, allocation,
and binding.
·
Real
time design methodology : This
course is aimed at developing real time (RT) applications. Petri nets and SART
methodology are investigated. VxWorks RT operating system (WindRiver)
is used for labs.
ICT Master 2 students (embedded system
option), Hanoi, Vietnam, 2013