Emmanuel CASSEAU

INRIA/IRISA, UMR 6074
CAIRN
ENSSAT, 6 rue de Kerampont, BP 80518, 22305 LANNION Cedex
FRANCE

 

Contact      Casseau Emmanuel

Home page

http://perso.univ-rennes1.fr/emmanuel.casseau

Phone: 

+33 (0)2 96 46 91 76

e-mail:

to_remove_emmanuel.casseau@irisa.fr

 

 

Reasearch activities    Teaching activities

 

Emmanuel Casseau received his Ph.D Degree in Electronic Engineering from UBO University, Brest, France, in 1994 and the DEA (MS Degree) in Electronics in 1990. From 1994 to 1996 he was a research engineer in the French National Telecom School, ENST Bretagne, France, where he developed high-speed Viterbi decoder architectures for turbo-code VLSI implementations. From 1996 to 2006 he was an Associate Professor in the Electronic Department at the University de Bretagne Sud, Lorient, France, where he led the IP project of the Lester lab. He his currently a Professor in INRIA/IRISA Lab., ENSSAT Engineering School, University of Rennes1, Lannion, France. His research interests include system design, high-level synthesis, SoC design methodologies and video architecture/core design.

Reasearch activities :

Funding :

  • S2S4HLS (2009-2012) in collaboration with ST Microelectronics : High-level synthesis HLS tools start to be used for industrial designs. HLS is analogous to software compilation transposed to the hardware domain. From an algorithmic behavior of the specification, HLS tools automate the design process and generate a register transfer level RTL architecture taking into account user-specified constraints. However design performance still depends on designer's skill to write apropriate source code. S2S4HLS project intends to process source code transformations to guide synthesis and lead to more efficient designs.
  • ROMA (2007-2010): The ROMA project proposes to develop a reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its computing structure to video dedicated computation patterns that can be speed-up and/or power efficient. On the contrary of previous attempts to design reconfigurable processors, which have focused on the definition of complex interconnection network between simple operators, a pipeline-based of evolved low-power coarse grain reconfigurable operators is investigated to avoid traditional overhead, in reconfigurable devices, related to the interconnection network. The adaptation of the processor datapath can be done dynamically in case of several consecutive functions to speed. A particular attention is given to the operator such as their granularity to match the domain-specific (video) computation patterns as well as the number system and the word-length used for the representation of the data.

PhD students :

  • H. Yviquel (2010-2013) co-supervised by M. Raulet (IETR Rennes) : Video coding design framework based on SoC-based platforms. Keywords : Reconfigurable Video Coding (RVC), System on Chip (SoC), multimedia processing, algorithm/architecture matching.
  • C. Xiao (2009-2012) : Pattern-based digital design . Keywords : code transformation, algorithm/architecture matching, pattern identification.
  • T. Chabrier (2009-2012) co-supervised by A. Tisserand : Reconfigurable Arithmetic Units for Cryptoprocessors with Protection against Side Channel Attacks. Keywords : arithmetic operator design, cryptography.
  • A. Banciu (2008-2011) : New digital design methodology for multi giga bits/s tranceivers. In collaboration with ST Microelectronics. Keywords : code transformation, high-level synthesis based design.
  • C. Palud (2008-2011) co-supervised by O. Sentieys : Reconfigurable video architecture design. Keywords : architecture design, video processing.

PhD graduates :

  • S. Khan (2007-2010) : Development Of High Performance Hardware Architectures For Multimedia Applications. Keywords : multimedia applications, subword parallelism (SWP), VLSI design. 
  • C. Andriamisaina (2005-2008) : Multimode system design. Keywords : high-level synthesis, multimode system design, bit-width optimizations.
  •  F. Abbes (2003-2007) : Virtual component integration. Keywords : communication interface, IP integration, system on chip
  •  S. Huet (2003-2006) : Interface constraint integration in plateform based design. Application to radiocommunication systems. Keywords : system-level design, HW communication refinement, rapid prototyping, electronic system-level (ESL) tool.
  •  B. Le Gal (2002-2005) : High-level synthesis for digital signal processing. Keywords : high-level synthesis, graph models, memory sequencer.
  •  F. Sayadi (2001-2006) : Voice decoder design. Keywords : G729, IP design, voice decoding.
  •  G. Savaton (1999-2002) : Behavioral virtual component design methodology for onboard signal processing. Keywords : behavioral IP reuse, JPEG2000, DWT.
  •  C. Jégo (1997-2000) : Architectural synthesis of digital processing applications dedicated to submicron technologies.

Selected papers

Teaching activities

Current taught modules :

  •  Signal processing : It covers the basics of discrete time-domain signal processing : Z-transform, Fourier transform, digital systems and sampling theory.
  •  Hardware description language : It introduces the main concepts behind HW description languages. VHDL is investigated. The course is split in two sections : VHDL for behavioral specification and VHDL for synthesis. Labs are based around the Quartus environment (Altera) and ModelSim.
  •  Real time design methodology : This course is aimed at developing RT applications. Petri nets and SART methodology are investigated. VxWorks RT operating system (WindRiver) is used for laboratories.